![]() 100k and 39k resistors form a voltage divider network to get the TTL level square wave down to an amplitude the ‘294 can handle without clipping. The last divider stage is a divide by two so the ‘294 filter sees a symmetrical square wave. This diagram shows the basic filter wiring. For this two channel build I would need a total of ten divide by ten stages, achievable with five 74hct390s. ![]() Cascading these gives a divide by ten with BCD output of the counter state. It’s a dual decade divider, each side has a divide by two, and a divide by five stage. I decided on the 74hct390 chip which I have used before. Internet searching did not turn up many choices for decade frequency dividers. Later on, this proved to be the most troublesome part of the project. To get line level output I decided to buffer the ‘294 output with an LM358 op amp connected as a voltage follower. The MAX294 has an uncommitted on board op amp but it is intended as a pre or post processing filter and has weak output specs. Diy word clock generator generator#When the signal generator display shows 25 megahertz, the output would be 25 kilohertz. ![]() If I add one additional decade to the ‘294 chip’s clock divide by 100 requirement, the total division would be 1000. That sixth requirement means decimal dividers throughout. Direct frequency readout from the signal generator display. Diy word clock generator portable#
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